GENIO 510 - norboot - falls back to Download-Mode instead booting again

Michael_Steinel · May 11, 2026, 12:36pm

Hello,

we currently do testing GENIO-510 norboot with reduced NOR size of 4MB.

The NOR is IS25LP032 and added to lk, bl2 and trusted-firmware-a recipies

with the following NOR layout:

CONFIG_MTDPARTS_DEFAULT=“mtdparts=nor0:512k(nor_bl2),2560k(nor_fip),512k(nor_dramk),256k(nor_env),256k(nor_misc)”

AB-boot and BL2 signing is disabled

Aftter flashing BL2 and u-boot they are booting as expected, but after a “reset” command in u-boot the SOC falls back to Download -Mode instead booting again!

Could you please give a hint what could be triggering this behaviour of ROM-bootloader ?

regards

Michael

pablo.sun · May 12, 2026, 5:59am

Hi @Michael_Steinel ,

It would be very helpful if we can have a bit more information:

Does this issue also occurs when you reboot in Linux console instead of U-Boot?
Would it be possible for you to provide the UART0 log between U-boot reset to the next download mode?

Michael_Steinel · May 13, 2026, 11:52am

Hello,

After flashing nor_bl2 and nor_fip

I attached a log of the “lk” flash process of “genio_flash nor_bl2
nor_fip” command.

The reboot after “lk” flash was done starts BL2 and U-Boot, but after
that only

Download Mode is seen in u-boot reset command or PCB power off/on !

Regards
Michael

(Attachment MTK_nor_boot_output_booting_to_uboot_2 )

[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[pmif_ulposc_cali] calibration fail: 0M
[pmif_clk_init] init fail
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:6 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:6 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:6 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:6 rdata = 0x0.
ERROR - calibration fail for spmi clk[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:7 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:7 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:7 rdata = 0x0.
[SPMI] check state 6 timeout over 1000
mt6315_read_check next, slvid:7 rdata = 0x0.
ERROR - calibration fail for spmi clk
 rst from: ?
MODE:          0x4d
STA:           0x0
LENGTH:        0xffe0
INTERVAL:      0xfff
SWSYSRST:      0x0
LATCH_CTL:     0x0
NONRST_REG:    0x0
NONRST_REG2:   0x0
DEBUG_CTL:     0x0
parse g_rgu_status: 0 (0x0)
[MEM] libdram version: 47a5a2a
[MEM] mt_get_ddr_gpio_trap_value : 17408 0
[MEM] dram_type = 9, channel: 4
[EMI] EMI_MPU_CTRL=0 1st
[EMI] EMI_MPU_CTRL=0 2nd
mtk_regulator_get 6315_6_buck3 fail
mtk_regulator_get 6315_6_buck4 fail
mtk_regulator_get vgpu11 fail
mtk_regulator_get vio18 fail
mtk_regulator_get vrf12 fail
[MEM] dramc_set_vio18_voltage 1800000(fixed to 1.8V)
[MEM] dramc_set_vmddr_voltage 750000
[MEM] dramc_set_vdd12_voltage 1200000
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 725000
[MEM] dramc_set_vddq_voltage 600000
[MEM] dramc_set_vdd2_voltage 1125000
[MEM] dramc_get_vio18_voltage 1800000(fixed to 1.8V)
[MEM] Vio18 = 1800000
[MEM] Vcore = -1
[MEM] dramc_get_vddq_voltage (pmic: RG value: -1)
[MEM] Vddq = -1
[MEM] vmddr = 0
[MEM] vdd12 = -2
[MEM] vdd2 = -1
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 637500
[EMI] CEN_CONA(0xf053f154),CEN_CONF(0x421000),CEN_CONH(0x44440003),CEN_CONK(0x71e30),▒▒(0x0)
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 637500
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] dramc_set_vcore_voltage data rate:3200, vcore: 687500
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:9, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:10, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:11, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:12, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:13, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:14, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:15, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:16, err_cnt:0
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:17, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:18, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:19, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:20, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:21, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:22, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:23, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:24, err_cnt:0
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] dramc_set_vddq_voltage 600000
[MEM] dramc_get_vddq_voltage (pmic: RG value: -1)
[MEM] Vddq = -1
[MEM] Vcore = -1
base init: MT8370 platform
[MEM] 1st complex R/W mem test pass (start addr:0x40000000)
[MEM] mt_mem_init(): done
[MEM] DDR frequency: 3733MHz
[EMI] DRAM rank0 size:0x100000000,
[EMI] DRAM rank1 size=0x100000000
[MEM] Memory size: 0x200000000(8192MB)
version:
        arch:     arm64
        platform: mediatek
        target:   mt8390-evk-norboot
        project:  mt8390-evk-norboot
        buildid:  -gef1457c7-dirty
Caps: 13b:57
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
phase: [map:ffffffff] [maxlen:32] [final:10]
Final cmd pad delay: a
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
Unimplemented: SEND_TUNING
phase: [map:ffffffff] [maxlen:32] [final:10]
Final data pad delay: a
[eMMC] Size: 29656 MB, Max.Speed: 200000 kHz, blklen(512), nblks(60735488), ro(0)
Caps: 13b:57
Caps: 13b:57
Caps: 13b:57
Caps: 13b:57
[SNFC] Flash ID: 0x9d 0x60 0x16
[SNFC] IS25LP032 chip_size = 0x400000 sect_size = 0x1000
starting app fitboot
block devices:
        mmc0, size 31096569856, bsize 512, ref 11, label <null> (no erase geometry)

        mmc0p1, size 4194304, bsize 512, ref 1, label bootloaders (no erase geometry)

        mmc0p2, size 4194304, bsize 512, ref 1, label bootloaders_b (no erase geometry)

        mmc0p3, size 33554432, bsize 512, ref 1, label firmware (no erase geometry)

        mmc0p4, size 33554432, bsize 512, ref 1, label firmware_b (no erase geometry)

        mmc0p5, size 524288, bsize 512, ref 1, label dramk (no erase geometry)

        mmc0p6, size 1048576, bsize 512, ref 1, label misc (no erase geometry)

        mmc0p7, size 33554432, bsize 512, ref 1, label bootassets (no erase geometry)

        mmc0p8, size 104857600, bsize 512, ref 1, label EFI_system_partition (no erase geometry)

        mmc0p9, size 33554432, bsize 512, ref 1, label kernel (no erase geometry)

        mmc0p10, size 7662690304, bsize 512, ref 1, label rootfs (no erase geometry)

        mmc0boot0, size 4194304, bsize 512, ref 1, label <null> (no erase geometry)

        mmc0boot1, size 4194304, bsize 512, ref 1, label <null> (no erase geometry)

        mmc0rpmb, size 4194304, bsize 512, ref 2, label <null> (no erase geometry)

        nor0, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

        nor_bl2, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

        nor_fip, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

        nor_dramk, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

        nor_misc, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

        nor_env, size 4194304, bsize 4096, ref 1, label <null> (no erase geometry)

fastboot_init()
[USB] U2 pullup D+
[USB] HS (2) is detected
[USB] usb_online: 1
fastboot: processing commands
fastboot: getvar:product[len:14]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:product]
fastboot: getvar:version[len:14]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:version]
fastboot: getvar:version-bootloader[len:25]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:version-bootloader]
fastboot: getvar:serialno[len:15]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:serialno]
fastboot: getvar:secure[len:13]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:secure]
fastboot: getvar:has-slot:nor_bl2[len:23]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:has-slot:nor_bl2]
fastboot: getvar:max-download-size[len:24]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:max-download-size]
fastboot: getvar:is-logical:nor_bl2[len:25]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:getvar:]-[arg:is-logical:nor_bl2]
fastboot: download:00042ae8[len:17]
fastboot:[download_base:0xffff000300000000][download_size:0x0]
fastboot:[cmd:download:]-[arg:00042ae8]
fastboot: flash:nor_bl2[len:13]
fastboot:[download_base:0xffff000300000000][download_size:0x42ae8]
fastboot:[cmd:flash:]-[arg:nor_bl2]
cmd_flash: nor_bl2, 273128
[SNFC] NOR erase offset=0x0 size=0x80000
[SNFC] NOR write offset=0x0 size=0x42ae8
fastboot: getvar:has-slot:nor_fip[len:23]
fastboot:[download_base:0xffff000300000000][download_size:0x42ae8]
fastboot:[cmd:getvar:]-[arg:has-slot:nor_fip]
fastboot: getvar:max-download-size[len:24]
fastboot:[download_base:0xffff000300000000][download_size:0x42ae8]
fastboot:[cmd:getvar:]-[arg:max-download-size]
fastboot: getvar:is-logical:nor_fip[len:25]
fastboot:[download_base:0xffff000300000000][download_size:0x42ae8]
fastboot:[cmd:getvar:]-[arg:is-logical:nor_fip]
fastboot: download:001cf655[len:17]
fastboot:[download_base:0xffff000300000000][download_size:0x42ae8]
fastboot:[cmd:download:]-[arg:001cf655]
fastboot: flash:nor_fip[len:13]
fastboot:[download_base:0xffff000300000000][download_size:0x1cf655]
fastboot:[cmd:flash:]-[arg:nor_fip]
cmd_flash: nor_fip, 1898069
[SNFC] NOR erase offset=0x80000 size=0x280000
[SNFC] NOR write offset=0x80000 size=0x1cf655
fastboot: reboot[len:6]
fastboot:[download_base:0xffff000300000000][download_size:0x1cf655]
fastboot:[cmd:reboot]-[arg:]
rebooting the device

F0: 102B 0000
F1: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0C00 0241 [0000]
G0: 1190 0000
EC: 0000 0000 [1000]
T0: 0000 0107 [1010]
Jump to BL

NOTICE:  BL2: v2.6(release):fa2f080bc-dirty
NOTICE:  BL2: Built : 05:09:44, May 16 2025
NOTICE:  WDT: Status = 0x40000000
NOTICE:  WDT: Last reset was normal software reboot
PLL init start...
PLL init done!
MTCMOS init start...
MTCMOS init done!
switch to 26MHz
ARMPLL_LL switch to OPP 0
switch to ARMPLL_LL
ARMPLL_LL_CON1: 0x133b14
abist meter[42], timeout
[PWRAP] pwrap_init_preloader
[PWRAP] is_pwrap_init_done 0
[PWRAP] pwrap_init start!!!!!!!!!!!!!
[PWRAP] Reset SPISLV ok
[PWRAP] Set Read Dummy Cycle ok
[PWRAP] _pwrap_init_dio ok
[PWRAP] _pwrap_init_reg_clock ok
[PWRAP] __pwrap_InitSPISLV ok
[PWRAP] si_sampling_ck_dly = 0, si_sampling_ck_pol = 0
[PWRAP] si_sample_ctrl = 0, rdata = d6a9
[PWRAP] First Valid Sampling Clock Found!!!
[PWRAP] si_sampling_ck_dly = 0, si_sampling_ck_pol = 1
[PWRAP] si_sample_ctrl = 20, rdata = 5aa5
[PWRAP] si_dly = 0, *RG_SPI_CON2 = 0, rdata = 1b27
[PWRAP] si_dly = 1, *RG_SPI_CON2 = 1, rdata = 1b27
[PWRAP] si_dly = 2, *RG_SPI_CON2 = 2, rdata = 1b27
[PWRAP] si_dly = 3, *RG_SPI_CON2 = 3, rdata = 1b27
[PWRAP] si_dly = 4, *RG_SPI_CON2 = 4, rdata = 1b27
[PWRAP] si_dly = 5, *RG_SPI_CON2 = 5, rdata = 1b27
[PWRAP] Data Boundary is Found !!!
[PWRAP] si_dly = 6, rdata = 1a65
[PWRAP] si_sample_ctrl=0x20(before)
[PWRAP] si_sample_ctrl=0x40(after)(non-FPGA)
[PWRAP] SI Strobe Calibration For PMIC 0 Done
[PWRAP] si_sample_ctrl = 40, si_dly = 6
[PWRAP] _pwrap_init_sistrobe Read Test ok
[PWRAP] _pwrap_init_sistrobe ok
[PWRAP] _pwrap_lock_SPISLVReg ok
[PWRAP] _pwrap_wacs2_write_test ok
[PWRAP] _pwrap_InitStaUpd ok
[PWRAP] write MODEM_TEMP_SHARE_CTRL start
[PWRAP] write MODEM_TEMP_SHARE_CTRL ok
[PWRAP] MODEM_TEMP_SHARE_CTRL:0
[PWRAP] PMIF_SPI_PMIF_MPU_CTRL = 0x34
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_START = 0x600
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_END = 0x67e
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_PER = 0xff3ffffb
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_START = 0x800
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_END = 0x13fe
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_PER = 0xfffcfff8
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_START = 0x1400
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_END = 0x207e
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_PER = 0xfffcfff0
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_START = 0x2080
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_END = 0x26fe
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_PER = 0xfffcff38
[PWRAP] _pwrap_config_mpu ok
[PWRAP] start pwrap_read_test
[PWRAP] rdata=0x5aa5
[PWRAP] Read Test pass, return_value = 0x0
[PWRAP] start pwrap_write_test
[PWRAP] after pwrap_write_test
[PWRAP] rdata=0xa55a (read back)
[PWRAP] Write Test pass
[PWRAP] channel pass
[PWRAP] REC_CMD0:0x0 (The last one adr)
[PWRAP] REC_WDATA0:0x0 (The last one wdata)
[PWRAP] REC_CMD1:0x0 (The second-last adr)
[PWRAP] REC_WDATA1:0x0 (The second-last wdata)
[PWRAP] REC_CMD2:0x0 (The third-last adr)
[PWRAP] REC_WDATA2:0x0 (The third-last wdata)
[PWRAP] REC_CMD3:0x0 (The fourth-last adr)
[PWRAP] REC_WDATA3:0x0 (The fourth-last wdata)
[PWRAP] REC_CMD4:0x0 (The fifth-last adr)
[PWRAP] REC_WDATA4:0x0 (The fifth-last wdata)
[PWRAP] REC_CMD5:0x0 (The sixth-last adr)
[PWRAP] REC_WDATA5:0x0 (The sixth-last wdata)
[PWRAP] enable spi debug ok
[PWRAP] clear record command ok
[PWRAP] PMIC_WRAP_MONITOR_MODE = Logging Mode
[PWRAP] PMIF_SPI_PMIF_MONITOR_CTRL = 0x5
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_0 = 0x1fbfff
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_0 = 0x0
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_0 = 0x0
[PWRAP] init pass, ret=0.
[PMIC] latch VCORE(VGPU11) 400000 uV(0x0)
[PMIC] latch VPU(VPROC1) 400000 uV(0x0)
[PMIC] latch VMDLA(VPROC2) 400000 uV(0x0)
[PMIC] latch VPROC(VCORE) 506250 uV(0x0)
[PMIC] latch VSRAM_PROC1 850000 uV(0x24)
[PMIC] latch VSRAM_PROC2 850000 uV(0x24)
[PMIC] latch VSRAM_GPU(VSRAM_OTHERS) 850000 uV(0x24)
[PMIC] latch VSRAM_APU(VSRAM_MD) 750000 uV(0x3c)
ERROR:   Only one SPI device is currently supported
[MEM] libdram version: 47a5a2a
[MEM] init partition address is 0x1400000
[MEM] mt_get_ddr_gpio_trap_value : 17408 0
[MEM] dram_type = 9, channel: 4
[EMI] EMI_MPU_CTRL=0 1st
[EMI] EMI_MPU_CTRL=0 2nd
[MEM] dramc_set_vio18_voltage 1800000(fixed to 1.8V)
[MEM] dramc_set_vmddr_voltage 750000
[MEM] dramc_set_vdd12_voltage 1200000
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 725000
[MEM] dramc_set_vddq_voltage 600000
[MEM] dramc_set_vdd2_voltage 1125000
[MEM] dramc_get_vio18_voltage 1800000(fixed to 1.8V)
[MEM] Vio18 = 1800000
[MEM] Vcore = 725000
[MEM] dramc_get_vddq_voltage (pmic: RG value: 600000)
[MEM] Vddq = 600000
[MEM] vmddr = 0
[MEM] vdd12 = 1200000
[MEM] vdd2 = 1125000
[dramc] PL_VERSION is updated, erase the DRAM shu_data
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 637500
[EMI] CEN_CONA(0xf053f154),CEN_CONF(0x421000),CEN_CONH(0x44440003),CEN_CONK(0x0),CHN_CONA(0x444f051)
[MEM] dramc_set_vcore_voltage data rate:1600, vcore: 637500
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] dramc_set_vcore_voltage data rate:3200, vcore: 687500
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:9, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:10, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:11, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:12, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:13, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:14, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:15, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:16, err_cnt:0
[MEM] HW channel(0) Rank(0), TA2 pass, pass_cnt:17, err_cnt:0
[MEM] HW channel(0) Rank(1), TA2 pass, pass_cnt:18, err_cnt:0
[MEM] HW channel(1) Rank(0), TA2 pass, pass_cnt:19, err_cnt:0
[MEM] HW channel(1) Rank(1), TA2 pass, pass_cnt:20, err_cnt:0
[MEM] HW channel(2) Rank(0), TA2 pass, pass_cnt:21, err_cnt:0
[MEM] HW channel(2) Rank(1), TA2 pass, pass_cnt:22, err_cnt:0
[MEM] HW channel(3) Rank(0), TA2 pass, pass_cnt:23, err_cnt:0
[MEM] HW channel(3) Rank(1), TA2 pass, pass_cnt:24, err_cnt:0
[MEM] dramc_set_vcore_voltage data rate:3732, vcore: 725000
[MEM] dramc_set_vddq_voltage 600000
[MEM] dramc_get_vddq_voltage (pmic: RG value: 600000)
[MEM] Vddq = 600000
[MEM] Vcore = 725000
base init: MT8370 platform
[MEM] 1st complex R/W mem test pass (start addr:0x40000000)
[MEM] mt_mem_init(): done
[MEM] DDR frequency: 3733MHz
[EMI] DRAM rank0 size:0x100000000,
[EMI] DRAM rank1 size=0x100000000
[MEM] Memory size: 0x200000000(8192MB)
NOTICE:  BL2: Booting BL31
NOTICE:  MT8188 mcupm_init
NOTICE:  mtk_init_mcu: Loaded (and reset) mcupm.bin: (119968 bytes)
NOTICE:  MT8188 sspm_init
NOTICE:  mtk_init_mcu: Loaded (and reset) sspm.bin: (137348 bytes)
NOTICE:  MT8188 dpm_init
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.dm: (422 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.pm: (18910 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.dm: (422 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.pm: (18910 bytes)
NOTICE:  SPM: binary array size = 0xa15
NOTICE:  SPM: spmfw version: pcm_suspend_20220705_v2_MP
NOTICE:  spm_kick_im_to_fetch: ptr = 0x94616010, pmem/dmem words = 0xa00/0x15
NOTICE:  mtk_init_mcu: Loaded (and reset) spm_firmware: (10384 bytes)
NOTICE:  BL31: v2.6(release):fa2f080bc-dirty
NOTICE:  BL31: Built : 05:09:44, May 16 2025
NOTICE:  [APUSYS]PLL init for mt8370, __apu_pll_init 136 --
NOTICE:  [APUSYS]__apu_buck_off_cfg 247 ++
NOTICE:  [APUSYS]__apu_buck_off_cfg 266 --
...

<debug_uart>


U-Boot 2022.10-ged8ae1daa1 (Dec 10 2025 - 01:49:50 +0000)

CPU:   MediaTek MT8370
DRAM:  8 GiB
Enabling SCP SRAM
Core:  140 devices, 24 uclasses, devicetree: separate
MMC:   mmc@11230000: 0, mmc@11240000: 1
Loading Environment from SPIFlash... spi frequency: 52000000 Hz
SF: Detected is25lp032 with page size 256 Bytes, erase size 64 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

Warning: device tree node '/config/environment' not found
In:    serial@11001100
Out:   serial@11001100
Err:   serial@11001100
Net:
Error: ethernet@11021000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:8...
** Unable to read file ubootefi.var **
Failed to load EFI variables
mtk_power_domain power-controller@10006000: vppsys0@15: failed to get subsys clk at index 28: -2
mtk_power_domain power-controller@10006000: failed to add child domain: vppsys0@15
mtk_power_domain power-controller@10006000: pextp-mac-p0@5: failed to get subsys clk at index 1: -2
mtk_power_domain power-controller@10006000: failed to add child domain: pextp-mac-p0@5
mtk_power_domain power-controller@10006000: csirx-top@7: failed to get clk at index 2: -2
mtk_power_domain power-controller@10006000: failed to add child domain: csirx-top@7
mtk_power_domain power-controller@10006000: adsp-ao@10: failed to get clk at index 2: -2
mtk_power_domain power-controller@10006000: failed to add child domain: adsp-ao@10
mtk_power_domain power-controller@10006000: ether@8: failed to get clk at index 1: -2
mtk_power_domain power-controller@10006000: failed to add child domain: ether@8

Error: ethernet@11021000 address not set.
mtk_power_domain power-controller@10006000: vppsys0@15: failed to get subsys clk at index 28: -2
mtk_power_domain power-controller@10006000: failed to add child domain: vppsys0@15
mtk_power_domain power-controller@10006000: pextp-mac-p0@5: failed to get subsys clk at index 1: -2
mtk_power_domain power-controller@10006000: failed to add child domain: pextp-mac-p0@5
mtk_power_domain power-controller@10006000: csirx-top@7: failed to get clk at index 2: -2
mtk_power_domain power-controller@10006000: failed to add child domain: csirx-top@7
mtk_power_domain power-controller@10006000: adsp-ao@10: failed to get clk at index 2: -2
mtk_power_domain power-controller@10006000: failed to add child domain: adsp-ao@10
mtk_power_domain power-controller@10006000: ether@8: failed to get clk at index 1: -2
mtk_power_domain power-controller@10006000: failed to add child domain: ether@8

Error: ethernet@11021000 address not set.
BootOrder not defined
EFI boot manager: Cannot load any image
Scanning mmc 0:a...
BootOrder not defined
EFI boot manager: Cannot load any image
=> setenv -f ethaddr 00:06:1F:00:00:00
=> setenv serverip 192.168.3.35
=> setenv vcserverip 192.168.3.35
=> setenv ipaddr   192.168.3.15
=> setenv bootargs " ${bootargs} root=PARTLABEL=rootfs rootwait"
=> env save
Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
OK
=> reset
resetting ...
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701
[DL] 00009C40 00000000 010701

Michael_Steinel · May 13, 2026, 12:32pm

Hello,

I think I found a problem with the NOR sector_size in “lk” its set to 0x1000 but the erase sector size should be 0x10000 for this NOR flash!

Currently I am investigating if this is the cause of “falling back to download mode”

Regards

Michael

Topic		Replies	Views
Genio 520 EVK stuck rebooting Yocto	5	150	December 17, 2025
Build Genio 720/520 EVK Images from Latest IoT Yocto v25.1-dev Announcements IoT-Yocto , Genio-520 , Genio-720	25	3238	December 31, 2025
Unable to flash Android pre-build image on windows General Discussion Genio-720	21	322	April 8, 2026
Development Status for IoT Yocto v25.1-dev Announcements IoT-Yocto , Genio-520 , Genio-720	13	2795	December 31, 2025
How to enable and use I2C2 (Raspberry Pi–style header) on Genio-510 EVK? Yocto Genio-510	7	128	December 1, 2025

GENIO 510 - norboot - falls back to Download-Mode instead booting again

Related topics