We are currently evaluating DMABUF for an RTSP IP camera pipeline on IoT Yocto Genio 520.
According to the following documentation, USB UVC cameras should use MMAP because using DMABUF may cause cache coherency issues and result in corrupted or dirty images:
Our use case is an RTSP IP camera rather than a USB UVC camera. Could you please confirm:
Does the same cache coherency or dirty-image risk apply to RTSP IP camera pipelines using DMABUF?
Is DMABUF officially supported for RTSP decoding and V4L2 frame processing on IoT Yocto?
Are any additional cache synchronization or GStreamer settings required?
To clarify the root cause of the dirty-image issue with USB UVC cameras: the UVC driver uses the CPU to assemble incoming USB packets into a frame buffer. Since neither the UVC driver nor the downstream MDP driver flushes the CPU cache back to DRAM, the MDP hardware may read stale (dirty) data, which results in the corrupted or dirty images described in the documentation.
Regarding your questions:
Does the same risk apply to RTSP IP camera pipelines using DMABUF? The risk applies only when the frame data is touched (written) by the CPU without a subsequent cache flush before the hardware (e.g., MDP) accesses it. For an RTSP IP camera pipeline, if any stage processes the buffer with the CPU, you must ensure the buffer is flushed to DRAM before MDP processing. If the data path is fully hardware-based (e.g., decoded and processed without CPU involvement), the coherency issue described for UVC does not apply in the same way.
Is DMABUF officially supported for RTSP decoding and V4L2 frame processing on IoT Yocto? To be transparent, RTSP IP cameras are not part of the official IoT Yocto feature list, so we don’t have a validated reference for this specific use case. If your camera relies on a generic/common V4L2 driver (similar to how UVC works), we’d recommend verifying that driver’s cache-handling behavior on your side, as the same coherency considerations described above would apply.
Are any additional cache synchronization or GStreamer settings required? Whenever the CPU writes to a buffer that will later be consumed by hardware, an explicit cache flush/sync is required to guarantee the hardware reads valid data. GStreamer will not automatically flush the cache when both drivers exchange buffers via DMABUF, so please check whether your pipeline elements expose a “force flush” or equivalent cache-sync option.