I just flashed the pre-built Android 14 image to the Genio 510 EVK. However, I can only see partial of the debug message through the UART0 port and the last line of message shows that “Log Turned Off.” Is it possible to turn the log on to show full debug message?
Hi Leo,
Welcome to the Genio community! We’re excited to have you on board.
How to Turn On Debug Log on Genio 510 (Pre-built Android Image)
1. Temporary (Runtime) Enable: Kernel Messages
Open a shell via UART0 or adb and run:
echo 8 > /proc/sys/kernel/printk
Note: This enables full kernel debug messages on the serial console, lasts until the next reboot.
2. Permanent (Persistent) Enable: Edit U-Boot bootargs
- Stop at U-Boot prompt during boot (UART0).
- Check current boot arguments:
printenv bootargs - Add high log level (
loglevel=8):
Replacesetenv bootargs <existing_bootargs> loglevel=8<existing_bootargs>with your current bootargs. - Save & reboot:
saveenv reset
3. Show Android Logs: logcat
To display Android user logs, type:
logcat
Press
Ctrl+Cto stop.
4. Reference Table
| Method | Persistent | Steps | Shows |
|---|---|---|---|
echo to /proc/sys/... |
No | echo 8 > /proc/sys/kernel/printk |
Kernel logs (temp) |
U-Boot bootargs edit |
Yes | Add loglevel=8 to bootargs, saveenv |
Kernel logs (always) |
logcat |
Session | logcat |
Android user-space logs |
Please let me know if this takes care of the issue—or if you run into any trouble, feel free to ask!
Thanks,
Santosh
Hi Santosh,
Thanks for your response!
The following log is the full debug message during boot from the UART0. It seems like there is neither u-boot prompt nor Linux kernel message output. The UART0 console does not accept any input after boot up thus I am not able to control the kernel parameters. Is there any other way to turn the log on?
PPL_LOG_STORE: check once, sig value 0x2FEDDB1F, addr 0x116000.
PL_LOG_STORE:sram->sig value 0x30D7B2F1!
PL_LOG_STORE:sram header is not match, format all!
PL_LOG_STORE:set ram_header->sig = 0xABCD1234
LL init start...
PLL init done!
MTCMOS init start...
MTCMOS init done!
#T#PLL=22
DISP PL IOMMU: (0x0, 0x0, 0x0, 0x0)
SUBDISP: LARB2: PORT2=0, PORT3=0
SUBDISP: LARB3: PORT2=0, PORT3=0
#T#GPIO=2
[RGU] rst from: ?
[RGU] STA from reg: 0x0
[RGU] MODE: 0x4D
[RGU] STA: 0x0
[RGU] LENGTH: 0xFFE0
[RGU] INTERVAL: 0xFFF
[RGU] SWSYSRST: 0x0
[RGU] LATCH_CTL: 0x0
[RGU] LATCH_CTL2: 0x0
[RGU] NONRST_REG: 0x0
[RGU] NONRST_REG2: 0x20000000
[RGU] REQ_MODE: 0x3F80FB
[RGU] REQ_IRQ_EN: 0x3F80FF
[RGU] DEBUG_CTL: 0x0
[RGU] parse g_rgu_status: 0 (0x0)
[RGU] Set NONRST_REG to 0x0
[RGU] mtk_wdt_mode_config mode value=34, tmp:22000034
[DOE_ENV]get_env apwdt_en
[RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2)
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x0
[RGU] rgu_update_reg: 0, bits: 0x300, addr: 0x100070A0, val: 0x0
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL2(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_LATCH_CTL(0x21E71)
[RGU] mtk_wdt_pre_init: MTK_WDT_REQ_MODE(3F00F2), MTK_WDT_REQ_IRQ_EN(3B00F0)
#T#WDT_PRE=12
RAM_CONSOLE using SRAM
RAM_CONSOLE start: 0x11D000, size: 0x800, sig: 0xE3F851E8
RAM_CONSOLE init done
RAM_CONSOLE wdt status (0x0)=0x0
#T#Ram console=2
abist meter[42], timeout
[PMIF] Using sw calibration!
[PMIF] Disable clock_monitor
[PMIF] ULPOSC1 K done: 260M, PLL_ULPOSC1_CON0/1/2 0x3CA54B 0x2900 0x41
[PMIF] Enable clock_monitor
[PMIF] [pmifclkmgr_set_clk] CLK_CFG_9 = 2010400
[pmifclkmgr_set_spmi_clk] done
[pmifclkmgr_set_spi_clk] done
#T#PMIFCLKMGR=5
[PMIF] pmif_spmi_force_normal_mode done
[SPMI] spmi_config_master CLK_CFG_17 = 3030400
[SPMI] IOCFG_LT_DRV_CFG3(11E10030) 0x10
[SPMI] IOCFG_LT_IES_CFG1(11E10080) 0xF7FFFFFF
[SPMI] IOCFG_LT_PD_CFG1(11E100B0) 0xFFE136
[SPMI] IOCFG_LT_PU_CFG1(11E100E0) 0x6C9
[SPMI] IOCFG_LT_RDSEL_CFG3(11E10140) 0x0
[SPMI] IOCFG_LT_SMT_CFG0(11E10160) 0xFFFFFFFF
[SPMI] IOCFG_LT_TDSEL_CFG3(11E101B0) 0x0
[SPMI] 653: spmi_read_check next, slvid:6 rdata = 0x2A.
[SPMI] spmi_read_check done, slvid:6
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
#T#SPMI=5
[PWRAP] pwrap_init_preloader
[PWRAP] is_pwrap_init_done 0
[PWRAP] pwrap_init start!!!!!!!!!!!!!
[PWRAP] Reset SPISLV ok
[PWRAP] Set Read Dummy Cycle ok
[PWRAP] _pwrap_init_dio ok
[PWRAP] _pwrap_init_reg_clock ok
[PWRAP] __pwrap_InitSPISLV ok
[PWRAP] si_sampling_ck_dly = 0, si_sampling_ck_pol = 0
[PWRAP] si_sample_ctrl = 0, rdata = D6A9
[PWRAP] First Valid Sampling Clock Found!!!
[PWRAP] si_sampling_ck_dly = 0, si_sampling_ck_pol = 1
[PWRAP] si_sample_ctrl = 20, rdata = 5AA5
[PWRAP] si_dly = 0, *RG_SPI_CON2 = 0, rdata = 1B27
[PWRAP] si_dly = 1, *RG_SPI_CON2 = 1, rdata = 1B27
[PWRAP] si_dly = 2, *RG_SPI_CON2 = 2, rdata = 1B27
[PWRAP] si_dly = 3, *RG_SPI_CON2 = 3, rdata = 1B27
[PWRAP] si_dly = 4, *RG_SPI_CON2 = 4, rdata = 1B27
[PWRAP] si_dly = 5, *RG_SPI_CON2 = 5, rdata = 1B27
[PWRAP] Data Boundary is Found !!!
[PWRAP] si_dly = 6, rdata = 804
[PWRAP] si_sample_ctrl=0x20(before)
[PWRAP] si_sample_ctrl=0x40(after)(non-FPGA)
[PWRAP] SI Strobe Calibration For PMIC 0 Done
[PWRAP] si_sample_ctrl = 40, si_dly = 6
[PWRAP] _pwrap_init_sistrobe Read Test ok
[PWRAP] _pwrap_init_sistrobe ok
[PWRAP] _pwrap_lock_SPISLVReg ok
[PWRAP] _pwrap_wacs2_write_test ok
[PWRAP] Enable CRC ok
[PWRAP] _pwrap_InitStaUpd ok
[PWRAP] write MODEM_TEMP_SHARE_CTRL start
[PWRAP] write MODEM_TEMP_SHARE_CTRL ok
[PWRAP] MODEM_TEMP_SHARE_CTRL:0
[PWRAP] PMIF_SPI_PMIF_MPU_CTRL = 0x34
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_START = 0x600
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_END = 0x67E
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_0_PER = 0xFF3FFFFB
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_START = 0x800
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_END = 0x13FE
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_1_PER = 0xFFFCFFF8
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_START = 0x1400
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_END = 0x207E
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_2_PER = 0xFFFCFFF0
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_START = 0x2080
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_END = 0x26FE
[PWRAP] PMIF_SPI_PMIF_PMIC_RGN_3_PER = 0xFFFCFF38
[PWRAP] _pwrap_config_mpu ok
[PWRAP] start pwrap_read_test
[PWRAP] rdata=0x5AA5
[PWRAP] Read Test pass, return_value = 0x0
[PWRAP] start pwrap_write_test
[PWRAP] after pwrap_write_test
[PWRAP] rdata=0xA55A (read back)
[PWRAP] Write Test pass
[PWRAP] channel pass
[PWRAP] REC_CMD0:0x0 (The last one adr)
[PWRAP] REC_WDATA0:0x0 (The last one wdata)
[PWRAP] REC_CMD1:0x0 (The second-last adr)
[PWRAP] REC_WDATA1:0x0 (The second-last wdata)
[PWRAP] REC_CMD2:0x0 (The third-last adr)
[PWRAP] REC_WDATA2:0x0 (The third-last wdata)
[PWRAP] REC_CMD3:0x0 (The fourth-last adr)
[PWRAP] REC_WDATA3:0x0 (The fourth-last wdata)
[PWRAP] REC_CMD4:0x0 (The fifth-last adr)
[PWRAP] REC_WDATA4:0x0 (The fifth-last wdata)
[PWRAP] REC_CMD5:0x0 (The sixth-last adr)
[PWRAP] REC_WDATA5:0x0 (The sixth-last wdata)
[PWRAP] enable spi debug ok
[PWRAP] clear record command ok
[PWRAP] PMIC_WRAP_MONITOR_MODE = Logging Mode
[PWRAP] PMIF_SPI_PMIF_MONITOR_CTRL = 0x5
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_0 = 0x1FBFFF
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_0 = 0x0
[PWRAP] PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_0 = 0x0
[PWRAP] init pass, ret=0.
#T#PWRAP=36
[TIA] trigger addr setup ok
[TIA] trigger value setup ok
[TIA] read back addr setup ok
[TIA] delay setup ok
[TIA] lock TIA_AUXADC register ok
[TIA] TIA init done
#T#TIA=2
Enter mtk_kpd_gpio_set!
Log Turned Off.
Thanks,
Leo
Dear Leo,
Please be informed that the prebuilt Android images are “user images” with minimal debug enabled and no root permissions.
Could you please let us know the reason for enabling debug prints?
Thanks,
Santosh
Hi Santosh,
I got it, that means we need to build our customized image to enable debug message?
Actually, we just want to observe the behaviors during boot through the debug prints.
Thanks,
Leo
Hi Leo,
Yes, that’s correct. To observe the debug messages during boot, you’ll need to build a customized image with debug prints enabled.
Thanks,
Santosh