Genio 520 EVK stuck rebooting

Yocto
1

Hi, my Genio 520 dev kit is constantly rebooting.

I can successfully flash images to it, but it keeps rebooting constantly anyway. I also tried flashing the prebuilt image from https://download.mediatek.com/aiot/download/prebuilt/v25.1-pr/scarthgap_k6.6_v25.1_genio-720-evk-ufs_private_251123184709_dev.tar.gz but that didn’t seem to help either.

Is there anything I can do to restore the 520 dev kit to a working condition?

Below is the UART0 debug log.


...

<debug_uart>


U-Boot 2022.10-g1a6a54f07f (Oct 31 2025 - 01:47:21 +0000)

CPU:   MediaTek MT8371AV/AZA
DRAM:  8 GiB
Core:  142 devices, 25 uclasses, devicetree: separate
MMC:   mmc@11230000: 0, mmc@11240000: 1
Loading Environment from scsi... Device at ufshci@112b0000 up at:ufshcd-mtk ufshci@112b0000: [RX, TX]: gear=[4, 4], lane[2, 2], pwr[FAST MODE, FAST MODE], rate = 2
OK
Warning: device tree node '/config/environment' not found
In:    serial@11001000
Out:   serial@11001000
Err:   serial@11001000
u-boot env location detected: 10
Net:   
Error: ethernet@1101a000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0 
start: 0xffef0000, end: 0xfffcb2e8
text_start: 0x4c000000, text_end: 0x4c0db2e8
fdtsz: 0x83c8 (33736)
script: 0x4c0e36b0
run 'source 000000004c0e36b0'
## Executing script at 4c0e36b0
sha256+ sha256,rsa3072:u-boot-img- 
Device 2: (0:2) Vendor: WDC Prod.: SDINFDO4-128G Rev: 2218
            Type: Hard Disk
            Capacity: 122031.9 MB = 119.1 GB (31240191 x 4096)
... is now current device

scsi read: device 2 block # 52736, count 8192 ... �������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������NOTICE:  BL2: v2.6(release):b8800f4b0-dirty
NOTICE:  BL2: Built : 03:17:05, Nov 21 2025
NOTICE:  WDT: Status = 0x20800000
NOTICE:  WDT: Last reset was other reset type: 0x20800000
NOTICE:  Pll init start...
NOTICE:  ucSpare0=440000, ucSpare1=1c000, ucSpare2=400000, ucSpare3=400, ucSpare4=3200003
[dramc] dram_tpye: TYPE_LPDDR5.
NOTICE:  mt_get_storage_type : 0x0
NOTICE:  storage_tpye: UFS
NOTICE:  Pll init Done!!
[PMIF] ULPOSC1 K done: 258M, PLL_ULPOSC1_CON0/1/2 0x1380010 0x4000000 0x0
[PMIF] ULPOSC1 K done: 258M, PLL_ULPOSC1_CON0/1/2 0x1380010 0x4000000 0x0
[PMIF] ULPOSC1 K done: 258M, PLL_ULPOSC1_CON0/1/2 0x1380010 0x4000000 0x0
[PMIF] ULPOSC1 K done: 258M, PLL_ULPOSC1_CON0/1/2 0x1380010 0x4000000 0x0
[PMIF] ULPOSC1 K done: 258M, PLL_ULPOSC1_CON0/1/2 0x1380010 0x4000000 0x0
[PMIF] Using hw calibration!
[PMIF] Latest cmd lists before reboot
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[PMIF] [swinf:0, cmd:0x0, rw:0x0, slvid:0, bytecnt:0, (addr 0x0=0x0)]
[SPMI] spmi_cali_config_io input driving:8 set bit:3 clr bit4 IOCFG_DRV_CFG2_P 0x1b000
[SPMI] [CALI PASS] driving:8 dly:1 pol:0 sampl:0x1
[SPMI] spmi_init done
[PMIC]TOP_RST_STATUS[0x150]=0x48
[PMIC]PONSTS[0xc]=0x2
[PMIC]POFFSTS[0xe]=0x1
[PMIC]PG_SDN_STS0[0x16]=0xffff
[PMIC]PG_SDN_STS1[0x18]=0xfff8
[PMIC]OC_SDN_STS0[0x1a]=0x0
[PMIC]OC_SDN_STS1[0x1c]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1430]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1440]=0x7ff
[PMIC]THERMALSTATUS[0x1e]=0x0
[PMIC]STRUP_CON4[0xa1a]=0x0
[PMIC]STRUP_CON12[0xa12]=0x31e0
[PMIC]TOP_RST_MISC[0x14a]=0x204
[PMIC]TOP_CLK_TRIM[0x388]=0x6cc0
[pmic_check_rst] UVLO_RSTB
[PMIC]just_rst = 0
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e800860)=0x0 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x1 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x11 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x111 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x1111 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x11111 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x111111 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x1111111 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e800864)=0x11111111 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x2 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x32 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x432 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x5432 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x65432 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e800868)=0x765432 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x0 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x0 shift=19
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x400000 shift=22
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x2400000 shift=25
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x22400000 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e4)=0x22400000 shift=31
NOTICE:  set_uid2aid_remap 2 write(0x1e8008e8)=0x1 shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e8)=0xd shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e8)=0x6d shift=5
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e8)=0x46d shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e8)=0x246d shift=11
NOTICE:  set_uid2aid_remap 1 write(0x1e8008e8)=0x1646d shift=14
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=3
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=6
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=9
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=15
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=18
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=21
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=27
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a0)=0x0 shift=30
NOTICE:  set_uid2aid_remap 2 write(0x1e8008a4)=0x0 shift=1
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=1
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=7
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=10
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=13
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=19
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=22
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=25
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a4)=0x0 shift=31
NOTICE:  set_uid2aid_remap 2 write(0x1e8008a8)=0x0 shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=5
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=11
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=14
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=17
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=23
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=26
NOTICE:  set_uid2aid_remap 1 write(0x1e8008a8)=0x0 shift=29
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x1 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x9 shift=3
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x49 shift=6
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x249 shift=9
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x1249 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x9249 shift=15
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x49249 shift=18
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x249249 shift=21
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x1249249 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x9249249 shift=27
NOTICE:  set_uid2aid_remap 1 write(0x1e8008ac)=0x49249249 shift=30
NOTICE:  set_uid2aid_remap 2 write(0x1e8008b0)=0x0 shift=1
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x2 shift=1
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x12 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x92 shift=7
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x492 shift=10
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x2492 shift=13
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x12492 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x92492 shift=19
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x492492 shift=22
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x2492492 shift=25
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x12492492 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b0)=0x92492492 shift=31
NOTICE:  set_uid2aid_remap 2 write(0x1e8008b4)=0x0 shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x4 shift=2
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x24 shift=5
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x124 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x924 shift=11
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x4924 shift=14
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x24924 shift=17
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x124924 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x924924 shift=23
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x4924924 shift=26
NOTICE:  set_uid2aid_remap 1 write(0x1e8008b4)=0x24924924 shift=29
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x0 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x10 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x210 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x3210 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x43210 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x543210 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x6543210 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f0)=0x76543210 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0x8 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0x98 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xa98 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xba98 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xcba98 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xdcba98 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xedcba98 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f4)=0xfedcba98 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x0 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x10 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x210 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x3210 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x43210 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x543210 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x6543210 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008f8)=0x76543210 shift=28
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0x8 shift=0
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0x98 shift=4
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xa98 shift=8
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xba98 shift=12
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xcba98 shift=16
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xdcba98 shift=20
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xedcba98 shift=24
NOTICE:  set_uid2aid_remap 1 write(0x1e8008fc)=0xfedcba98 shift=28
NOTICE:  mminfra_init done
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS 1/2/3/4/7=2 2 2 2 2
clk_buf_dump_dts_log: PMIC_CLK_BUF?_OUTPUT_IMPEDANCE 1/2/3/4/7=6 4 4 4 4
clk_buf_dump_dts_log: PMIC_CLK_BUF?_CONTROLS_FOR_DESENSE 2/3/4=4 0 4
clk_buf_dump_clkbuf_log DCXO_CW00/09/12/13/15/19=0x6a4d 53f0 8180 4c f0f 924c
clk_buf_dump_clkbuf_log spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 1 1 1 1
clk_buf_dump_clkbuf_log clk buf vrfck_hv_en=0x0
[clk_buf_init_pmic_clkbuf] XO_SOC_VOTER(0x1)
[clk_buf_init_pmic_clkbuf] XO_WCN_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_NFC_VOTER(0x1)
[clk_buf_init_pmic_clkbuf] XO_CEL_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_EXT_VOTER(0x1)
clk_buf_dump_clkbuf_log DCXO_CW00/09/12/13/15/19=0x4a4d 51f0 8180 4c f0f 924c
clk_buf_dump_clkbuf_log spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 1 1 0 0
clk_buf_dump_clkbuf_log clk buf vrfck_hv_en=0x0
pmwrap_interface_init: PMIF_VLD_RDY
clk_buf_init_pmic_wrap: DCXO_CMD_ADR0/WDATA0=0x4580458/10000
clk_buf_init_pmic_wrap: DCXO_CMD_ADR1/WDATA1=0x78a078c/1000100
NOTICE:  mt_get_storage_type : 0x0
NOTICE:  storage_tpye: UFS
[dramc] init partition address is 0x4880000
[MEM] libdram version: 1170044
base init: MT8371 platform
[Dramc_Top] setup_dramc_voltage_by_pmic start!
[Dramc_Top] dramc_set_vcore_voltage :800000
[Dramc_Top] dramc_set_vmddr_voltage :856250
[Dramc_Top] dramc_set_vddq_voltage :500000
[Dramc_Top] dramc_set_vdd2H_voltage :1050000
[Dramc_Top] dramc_set_vio18_voltage :1800000
Setup Read voltage: Vdd1 = 1800000, Vcore = 800000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vcore_voltage :700000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 1600, shu = 3, Vdd1 = 1800000, Vcore = 700000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
DRAMK Version: 0x20250312
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1600, shu = 3, Vddq_level = 1, Vddq = 500000

[DRAM]ett_fix_freq = 255
gddrphyfmeter_value[3] = 0, return p->frequency
gddrphyfmeter_value[3] = 0, return p->frequency
RODTENSTB_EXT_ori_gary = 14
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 3200
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 19
gddrphyfmeter_value[3] = 0, return p->frequency
[DRAMC] dram_info.u8MR8Densit  0x100000000, i 0
[DRAMC] dram_info.u8MR8Densit  0x100000000, i 1
[DRAMC] dram_total_density  0x200000000
[DRAMC] dram_info u1DieNum 0: 1
[DRAMC] dram_info u1DieNum 1: 1
[DRAMC] dram_info u8MR8Density>1 0: 0x80000000
[DRAMC] dram_info u8MR8Density>1 1: 0x80000000
[DRAMC] dram_info u4RankNum 2
die_size = 0x0, dram_info = 0x10 dram_info->u1DieNum[0] = 1
[DRAMC] 0x80000010
die_size = 0x0, dram_info = 0x10 dram_info->u1DieNum[1] = 1
[DRAMC] 0x80000010
[Dramc_Top] dramc_set_vcore_voltage :700000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 1600, shu = 3, Vdd1 = 1800000, Vcore = 700000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
DRAMK Version: 0x20250312
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1600, shu = 3, Vddq_level = 1, Vddq = 500000

[DRAM]ett_fix_freq = 255
RODTENSTB_EXT_ori_gary = 14
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 3200
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 19
[Dramc_Top] dramc_set_vmddr_voltage :856250
[Dramc_Top] dramc_set_vmddr_voltage :856250
[Dramc_Top] dramc_set_vmddr_voltage :856250
[Dramc_Top] dramc_set_vmddr_voltage :856250
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1600, shu = 3, Vddq_level = 1, Vddq = 500000
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1600, shu = 3, Vddq_level = 1, Vddq = 500000


[Calibration Summary] Freqency 1600
CH 0, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 0, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

[Dramc_Top] dramc_set_vcore_voltage :675000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 1066, shu = 4, Vdd1 = 1800000, Vcore = 675000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1066, shu = 4, Vddq_level = 1, Vddq = 500000
gddrphyfmeter_value[4] = 0, return p->frequency
gddrphyfmeter_value[4] = 0, return p->frequency
RODTENSTB_EXT_ori_gary = 14
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 2133
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 19
gddrphyfmeter_value[4] = 0, return p->frequency
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1066, shu = 4, Vddq_level = 1, Vddq = 500000
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 1066, shu = 4, Vddq_level = 1, Vddq = 500000
2

UART0 debug log continued:


[Calibration Summary] Freqency 1066
CH 0, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 0, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : NO K
DUTY CYCLE MONITOR  : NO K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

[Dramc_Top] dramc_set_vcore_voltage :800000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 3200, shu = 0, Vdd1 = 1800000, Vcore = 800000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 3200, shu = 0, Vddq_level = 1, Vddq = 500000
gddrphyfmeter_value[0] = 0, return p->frequency
gddrphyfmeter_value[0] = 0, return p->frequency
RODTENSTB_EXT_ori_gary = 20
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 6400
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 25
gddrphyfmeter_value[0] = 0, return p->frequency
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 3200, shu = 0, Vddq_level = 1, Vddq = 500000
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 3200, shu = 0, Vddq_level = 1, Vddq = 500000


[Calibration Summary] Freqency 3200
CH 0, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : FAST K
RX RDQS DCC         : FAST K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 0, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : FAST K
RX RDQS DCC         : FAST K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : FAST K
RX RDQS DCC         : FAST K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : FAST K
RX RDQS DCC         : FAST K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

[Dramc_Top] dramc_set_vcore_voltage :762500
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 2750, shu = 1, Vdd1 = 1800000, Vcore = 762500, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2750, shu = 1, Vddq_level = 1, Vddq = 500000
gddrphyfmeter_value[1] = 0, return p->frequency
gddrphyfmeter_value[1] = 0, return p->frequency
RODTENSTB_EXT_ori_gary = 16
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 5500
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 21
gddrphyfmeter_value[1] = 0, return p->frequency
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2750, shu = 1, Vddq_level = 1, Vddq = 500000
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2750, shu = 1, Vddq_level = 1, Vddq = 500000


[Calibration Summary] Freqency 2750
CH 0, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 0, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

[Dramc_Top] dramc_set_vcore_voltage :725000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 2133, shu = 2, Vdd1 = 1800000, Vcore = 725000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2133, shu = 2, Vddq_level = 1, Vddq = 500000
gddrphyfmeter_value[2] = 0, return p->frequency
gddrphyfmeter_value[2] = 0, return p->frequency
RODTENSTB_EXT_ori_gary = 14
LP5_RODT_temp.RDQS_PST_gary = 0
LP5_RODT_temp.RDQS_PST_gary = 0
A_D->DQ_P2S_RATIO_gary = 8
DFS(group_id)->data_rate_gary = 4266
RODTENSTB_UI_OFFSET_gary = 12
RODTENSTB_EXT_pst_add_gary = 19
gddrphyfmeter_value[2] = 0, return p->frequency
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2133, shu = 2, Vddq_level = 1, Vddq = 500000
[Dramc_Top] dramc_set_vddq_voltage :500000
vSetVddqForLP5: Read voltage: freq = 2133, shu = 2, Vddq_level = 1, Vddq = 500000


[Calibration Summary] Freqency 2133
CH 0, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 0, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 0
SW Impedance        : PASS
8 Phase             : FAST K
DUTY Scan           : FAST K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : FAST K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : FAST K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : FAST K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

CH 1, Rank 1
SW Impedance        : PASS
8 Phase             : NO K
DUTY Scan           : NO K
ZQ Calibration      : PASS
Jitter Meter        : NO K
CBT Training        : NO K
Write leveling(PI)  : FAST K
Write leveling(DLY) : FAST K
DUTY CYCLE MONITOR  : FAST K
RX DQS gating       : FAST K
RX OFFC             : NO K
RX DQ/DQS(RDDQC)    : FAST K
RX DQ/DQS(RDDQC_DQM_ONLY) : FAST K
TX DQ/DQS           : FAST K
RX DATLAT           : NO K
RX DQ/DQS(Engine)   : FAST K
RX RDQS DCA         : NO K
RX RDQS DCC         : NO K
RX RDQ DCC          : NO K
TX OE               : NO K
All Pass.

HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
[emi_simple_cpu_mem_test] Vcore = 725000, Real Frequency = 4264, Ideal Frequency = 4266
[MEM_TEST] Rank 0 OK.(uiFixedAddr 0x!!! refresh interval > 4X
!!! refresh interval > 4X
HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
[emi_simple_cpu_mem_test] Vcore = 725000, Real Frequency = 4264, Ideal Frequency = 4266
[MEM_TEST] Rank 0 OK.(uiFixedAddr 0x
[DRAM] FINAL_SHU = 3 (gFreqTbl_lp5 index),ett_fix_freq = 255
[DFS_EN] ch[0] DFS - pingpong_shu_level = 0x1, sram_shu_level = 0x3
[DFS_EN] ch[0] Enter LP5 FASTK
[DFS_EN] ch[0] Enter LP5/LP4 TX retry
[DFSRuntimeMRWEn]
DFSRuntimeMRWEn: 531: [DFS_EN] ch[0] Update MR16...
DFSRuntimeMRWEn: 531: [DFS_EN] ch[1] Update MR16...
[DFS_EN] ch[0] DIS DFSNoQueueFlushWA
CTOGRP_CUR=0, CTOGRP_NEXT=0
DFSNoQueueFlushWA: NoQueueFlush DISABLE
[DFS_EN] ch[0] Exit LP4 TX retry
[Dramc_Top] dramc_set_vcore_voltage :700000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 1600, shu = 3, Vdd1 = 1800000, Vcore = 700000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[Dramc_Top] dramc_set_vcore_voltage :700000
[Dramc_Top] dramc_set_vmddr_voltage :856250
vSetVcoreByFreq: Read voltage: freq = 1600, shu = 3, Vdd1 = 1800000, Vcore = 700000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[DFS_EN] ch[0] DFS - pingpong_shu_level = 0x0, sram_shu_level = 0x3
[DFS_EN] ch[0] Enter LP5 FASTK
[DFS_EN] ch[0] Enter LP5/LP4 TX retry
[DFSRuntimeMRWEn]
DFSRuntimeMRWEn: 531: [DFS_EN] ch[0] Update MR16...
DFSRuntimeMRWEn: 531: [DFS_EN] ch[1] Update MR16...
[DFS_EN] ch[0] DIS DFSNoQueueFlushWA
CTOGRP_CUR=0, CTOGRP_NEXT=0
[DFS_EN] ch[0] Exit LP4 TX retry
HW channel(0) Rank(0), TA2 pass, pass_cnt:9, err_cnt:0
HW channel(0) Rank(1), TA2 pass, pass_cnt:10, err_cnt:0
HW channel(1) Rank(0), TA2 pass, pass_cnt:11, err_cnt:0
HW channel(1) Rank(1), TA2 pass, pass_cnt:12, err_cnt:0
[emi_simple_cpu_mem_test] Vcore = 700000, Real Frequency = 3088, Ideal Frequency = 3200
[MEM_TEST] Rank 0 OK.(uiFixedAddr 0x[Dramc_Top] dramc_set_vcore_voltage :725000
Restore Vcore = 725000
check_dramc_voltage_after_k: Read voltage: Vdd1 = 1800000, Vcore = 725000, Vddq = 500000, Vmddr = 856250, Vdd2H = 1050000, Vdd2L = 0
[MEM] normal_mem_init(): done
[MEM] mt_mem_init(): done
[MEM] Memory size: 0x200000000
ERROR:   BL2: Boot control is in trouble and rollback failure.
NOTICE:  BL2: Booting BL31
NOTICE:  CPU Segment ID: 0x81
ERROR:   mmap_add_region_check() failed. error -1
ERROR:   mmap_add_region_check() failed. error -1
ERROR:   mmap_add_region_check() failed. error -1
ERROR:   mmap_add_region_check() failed. error -1
ERROR:   mmap_add_region_check() failed. error -12
ERROR:   mmap_add_region_check() failed. error -12
ERROR:   mmap_add_region_check() failed. error -12
ERROR:   mmap_add_region_check() failed. error -12
ERROR:   mmap_add_region_check() failed. error -12
ERROR:   mmap_add_region_check() failed. error -12
NOTICE:  SPM: binary array size = 0xe12
NOTICE:  SPM: spmfw version: pcm_suspend_20250822    MediaTek SPM firmware: version 3.0
NOTICE:  spm_kick_im_to_fetch: ptr = 0x946191a0, pmem/dmem words = 0xe03/0xf
NOTICE:  mtk_init_mcu: Loaded (and reset) spm_firmware.bin: (14504 bytes)
NOTICE:  sspm_init
NOTICE:  mtk_init_mcu: Loaded (and reset) sspm.bin: (69928 bytes)
NOTICE:  dpm_init
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.dm: (1040 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.pm: (36624 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.dm: (1040 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) dpm.pm: (36624 bytes)
NOTICE:  mtk_init_mcu: Loaded (and reset) mcupm.bin: (142024 bytes)
NOTICE:  BL31: v2.6(release):b8800f4b0-dirty
NOTICE:  BL31: Built : 03:17:05, Nov 21 2025
...

<debug_uart>


U-Boot 2022.10-g1a6a54f07f (Oct 31 2025 - 01:47:21 +0000)

CPU:   MediaTek MT8371AV/AZA
DRAM:  8 GiB
Core:  142 devices, 25 uclasses, devicetree: separate
MMC:   mmc@11230000: 0, mmc@11240000: 1
Loading Environment from scsi... Device at ufshci@112b0000 up at:ufshcd-mtk ufshci@112b0000: [RX, TX]: gear=[4, 4], lane[2, 2], pwr[FAST MODE, FAST MODE], rate = 2
OK
Warning: device tree node '/config/environment' not found
In:    serial@11001000
Out:   serial@11001000
Err:   serial@11001000
u-boot env location detected: 10
Net:   
Error: ethernet@1101a000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0
3

Nevermind, it was a power supply issue :upside_down_face:

4

could I Know which power supply lead to this issue,tks.

5

Are you experiencing the 520 dev kit rebooting constantly?

In my case I was re-using a power supply from an older Genio 510 EVK. The plug-in cord had come loose from one end of the power brick (bottom right of picture), and I hadn’t noticed it. It looks similar to the picture below.

image
image752×746 75.6 KB

6

My device is G720 dev kit ,and rebooting constantly ; Analying the urat log, it was found that it is basically identical to the log you mentioned above,Maybe I need have a double check about power supply. Anyway, thank you very much for your reply.